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Also several experimental results have been published. Among them are investigations of geometrical optimization of InP DHBTs with regards to speed [27], [15]. Also, for other HBT technologies like SiGe and GaAs geometrical investigations have been conducted [112], [49], [103], [81]. In addition, experimental data regarding power performance and thermal resistance as functions of geometrical dimensions are available [109]. However, it is very difficult to calculate the optimum dimensions of InP DHBTs for a desired performance for the following reasons.

In addition, VCOs, multiplexers, and clock and data recovery circuits suited for 80 Gbit/s applications have been developed, using the 45 46 3. 1: Measured cut-off frequency fT of an InP-DHBT as a function of collector current density for different collector-to-emitter voltages. same model [73],[74],[72]. This shows that the modeling strategy described in this chapter is a suitable approach for the development of high-speed circuits for data rates at 80 Gbit/s and beyond. Content In the following section different large-signal models are discussed.

Process technology, the epitaxial layer structure and the geometrical dimensions have to be optimized. First, different epitaxial layers were investigated using high-frequency and dc measurements. From the results, improved layer structures could be designed. Second, the geometrical layout of the transistors was optimized by investigating different transistors manufactured on the 44 2. InP-based Double Heterojunction Bipolar Transistor optimized layer structure. As a result, InP DHBTs with high-frequency parameter values of more than 280 GHz for both fT and fmax could be realized, while maintaining a breakdown voltage of over 4 V.

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